The present invention disclosed herein relates to a direct memory access (DMA) controller and a data transmitting method of a direct memory access channel.
Real-time multimedia applications are becoming more and more important. The real-time multimedia applications require a very high data processing rate of thousands of megabits per second. For high data processing rates, some processing systems use the uniprocessing architecture and others use the multiprocessing architecture. In multiprocessing systems, most sub-processors operate in parallel or at least in cooperation in order to achieve desired processing results.
Recently, the state-of-the-art computer applications are more and more complicated to meet an ever-increasing demand for processing systems. There is therefore an ever-increasing demand for a higher computer data processing rate. For example, in order to achieve desired results, graphic applications require a very large amount of data access, data computation, and data manipulation within a relatively short time. Therefore, the graphic applications require the highest demand for processing systems.
A direct memory access (DMA) scheme is used in some processing systems. A computer structure of such processing systems is designed to directly transmit data between a device and a memory without including any microprocessor for data transmission. Such a computer structure generally includes a memory controller for receiving a data transmission command from a system device requesting data transmission. A typical DMA command specifies a data block size, a virtual start address in a data-transmitting system memory, and a start address of a data-receiving device.
A typical DMA scheme can increase a data processing rate in comparison with an indirect memory access technology, but still has various limitations. For example, one or more sub-processors are necessary for applications for computation such as graphic processing using a multiprocessing system. However, such sub-processors generate many DMA commands in order to achieve all DMA data transmissions, thus increasing the processor load and reducing the processing capability. Also, in the typical DMA scheme, a DMA controller controls data transmission between a peripheral device and a memory. However, the efficiency of DMA transmission between memories connected to independent buses is required in the recent media processors.